OpenOCD + Actel (Microsemi) CoreMP7
In my engineer degree work I used CoreMP7-enabled ProASIC3 Development Kit (part number M7A3P-DEV-KIT-SCS). In a time it was launched by Actel (acquired by Microsemi) it was one of the first attempts of creating a SoPC with soft ARM core available for wide market without royalties. This particular kit has M7A3P1000 chip with 484 balls, 1M system gates and can drive internal PLL up to 350 MHz, so it’s pretty powerful. There is 1 MB of on-board RAM and 16 MB of Intel FLASH.
ARM7TDMI-S processor itself is available as a compiled and pre-placed component that can be put into user system design in SmartDesign tool (part of Libero environment). Although one cannot simulate core directly due to the lack of HDL source files, there is a BFM script compiler which produces HDL testbenches simulating transfers over AHB system bus. User writes BFM (TCL-like) scripts as if they were processor read and write operations.
The board provides several ways of programming the device. FPGA configuration is loaded with on-board FlashPro3 programmer. The same tool can be used to program and debug software written for ARM processor via SoftConsole IDE (which is modified Eclipse software). Microsemi’s FlashPro3 debugger has serious limitation, however: it can only debug code running in RAM. It can program FLASH memory using additional application (cliarm.exe console) and on this its functionality ends. Producer didn’t left programmer without choice, there is additional JTAG header on board. It is called RV (RealView) header and can be connected with 20-wire (2×10) flat cable to regular JTAG programmer. This was the reason I installed and configured fresh Eclipse with CodeSourcery G++ Lite (now Mentor Graphics) version 2011.03-42 with GCC 4.5.2 and OpenOCD in version 0.4.0 (2010-02-22-19:05). Maybe in some further post I will discuss how to set up this environment, now let’s look how to connect a programmer to the ARM core.
I use device based on FT2232 (-C, -D, -L) chip, it is similar to Amontec JAGkey. This piece of hardware was designed by Freddie Chopin. It is has a standard JTAG dual-row pin header which easily connects with P3 connector on board:
M7A3P-DEV-KIT-SCS JTAG header schematics
The tricky part is how to connect the header to ARM processor. On the core side there are following connections:
SmartDesign CoreMP7Bridge
Note, that UJTAG group refers to the ports that have predefined physical design constraints – they are automatically connected in Designer I/O Attribute Editor. They serve as a JTAG connected to FlashPro3.
As you can see ports in RV_ICE_If group are not one-to-one compatible with pins on board. What you have to do is to make a HDL wrapper that will sort these pins and do some other actions to make things work. In this step extremely helpful was sample project distributed with board. Its sources are present on a CD or in ZIP downloaded from Actel’s website, in folder M7A3P_CDImage.zip/Disk1/Sample Design/. To get that idea look at file Hardware/Source/socTop.v. There is also an example on how to connect memories to CoreMemCtrl module.
Finally, I had to write OpenOCD configuration scripts. Traditionally, they are split in two: one referring to CPU-specific settings and second with settings related to board. Unlike in hard processor cores in CoreMP7 you are the one who designs memory map, so most probably both of these files must be altered before use. Be sure to read the comments!
coremp7.cfg
m7a3p_dev_kit_scs.cfg
If you read this you probably already know there’s not much information about designs in Actel/Microsemi devices in the Internet. Producer gives excellent documentation and examples, but that’s all. I am aware that my article hasn’t covered topic even in a small part. This FPGA/ARM7 board is also quite ancient device (odd, isn’t it? 2007 if I recall well…) and I have experience only with this specific one. But it finally worked, so feel free to encourage me to write more:-)